1. Field of the Invention
The present invention relates to a semiconductor device for power amplification, and more particularly, to arrangement of active regions and electrodes for power transistors.
2. Description of the Related Art
A power semiconductor device using compound semiconductor materials for various applications such as local ground stations of mobile telephone network requires characteristics of high-speed operation and low power consumption. FIGS. 1A and 1B are a top view and a cross-sectional view in a unit transistor region of a conventional power semiconductor device, respectively. Hereinafter, the same numerals are designated to the same elements in all figures. As shown in FIGS. 1A and 1B, a conventional field effect transistor for power amplification (or a power FET) comprises a parallel array of unit transistors 11 disposed in an active region 10 on a compound semiconductor substrate 15 such as gallium-arsenide (or GaAs), in which each of the unit transistors 11 has a gate finger 1, a drain finger 2 and a source finger 3. A gate bar 4 connects all of the gate fingers 1 to a gate pad 5 in parallel, a drain bar 6 connects all of the drain fingers 2 to a drain pad 7 in parallel connection and a source bar 8 connects all of the source fingers 3 to a source pad 9 in parallel connection. In this configuration of the power FET, the channel width must increase in order to increase the power amplification. However, the increase of the channel width needs the corresponding increase of the gate finger 1, a drain finger 2 and a source finger 3 lengthwise, which results in degradation of device characteristics due to increase of inner resistance of the respective fingers. To avoid this problem, it could be possible to increase the numbers of parallel transistors maintaining the channel width unchanged, by which the power amplification would be increased without increase of the inner resistance, but the increase of the numbers of parallel transistors by simple increase of the active region in the channel-length direction leads to increase in length of the respective bars, which results in an adverse effect that difference in distance from a pad to each of transistors increases because the distance depends upon relative disposition of the respective transistor to the pad. For this reason, the larger difference in the distance incurs more difficulty in a high-speed parallel operation.